Antonios N. Dadaliaris, Panagiotis Oikonomou, Maria G. Koziri, Evangelia Nerantzaki, Thanasis Loukopoulos, Georgios I. Stamoulis
Circuits and Systems , 8, 191-201.
Publication year: 2017

Standard cell placement algorithms have been at the forefront of academic research
concerning the physical design stages of VLSI design flows. The penultimate
step of a standard cell placement procedure is legalization. In this step
the manufacturability of the design is directly settled, and the quality of the
solution, in terms of wirelength, congestion, timing and power consumption
is indirectly defined. Since the heavy lifting regarding processing is performed
by global placers, fast legalization solutions are protruded in state-of-the-art
design flows. In this paper we propose and evaluate a legalization scheme that
surpasses in execution speed two of the most widely used legalizers, without
not only corrupting the quality of the final solution in terms of interconnection
wirelength but improving it in the process.