In a typical integrated circuit (IC) design flow, each step is executed sequentially, and valuable feedback is provided that can be utilized if we are forced to backtrack as a means to resolve problems or satisfy design constraints and restrictions. Following a similar logic, the objective of our algorithm is to plan the I/O pad positions, based on back-annotated data gathered from a formerly placed similar design, concerning the cell connectivity and positioning, in order to minimize the total wirelength, a critical metric defining the routability, and thus the manufacturability of a design. Our approach results in the embetterment of the wirelength at an acceptable runtime.