The major design challenges of ASIC design, like power dissipation, timing, voltage-drop, interconnect and reliability are tackled during the Physical Design phase of any flow. The placement procedure can significantly modify parts of the design and consequently metrics relevant to the aforementioned challenges. Text reports cannot always generate useful insight based solely on these metrics. Design visualization can be of utmost importance in deciding if the placement strategy followed is leading to fruition. In this paper we present a placement visualizer/analyzer that helps capture the most critical aspects of a placed design and empowers the user to draw safer conclusions concerning the quality of the final result.