Mantos, K., Koungalis, N., Demesiotis, G., Oikonomou, P., Dadaliaris, A. N., & Stamoulis, G. I
Proceedings of the 21st Pan-Hellenic Conference on Informatics (p. 16). ACM
Publication year: 2017

One of the most important stages of a typical ASIC (Application-specific integrated circuit) design flow, is physical design. The most prominent step of the aforementioned stage is placement. Major design challenges are regulated while traversing this stage in order to accommodate the final sign-off. Various aspects of the design might be modified during this step, and the primary manner to keep track of these modifications is usually through detailed text reports, concerning universal metrics like density and wire-length, and generic static visualizations, due to the timing overhead it introduces to the overall procedure. However, a detailed and interactive depiction of the final result might provide insights concerning the quality of the final solution and the effectiveness of the applied algorithms. In this paper we present WEVIAN, a web-based placement visualizer/analyzer that enhances the design procedure by adding interactivity and offloading part of the workload to a third-party server.

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