Antonios N Dadaliaris, Panagiotis Oikonomou, Maria G Koziri, Evangelia Nerantzaki, Yannis Hatzaras, Dimitrios Garyfallou, Thanasis Loukopoulos, Georgios I Stamoulis
Journal of Low Power Electronics
Publication year: 2017

As process minimum feature sizes shrink, interconnect capacitance becomes a larger
proportion of the total switched capacitance, thus standard cell and component placement
increasingly affects power consumption. Therefore, minimizing the total interconnect wire
length becomes a power reduction exercise as well. The final step of a standard cell
placement process consists of legalization where the target is to eliminate overlaps as well
as aligning cell positions to eligible rows. The simplest, yet fastest method in the literature