Abstract Voltage drop on the power supply network is an issue of ultimate importance in
integrated circuit (IC) fabrication processes as we move beyond the 30nm technology
barrier, affecting both timing and reliability. We propose an evolved variation of our previous
placer that can achieve more balanced results concerning the timing of the critical path and
the total wire-length of a design. The placer works incrementally to existing placers and is,
thus easier to integrate into existing design flows. Keywords: Algorithms, physical design, …